Comparative Analysis of Fully Convolutional Networks (FCN), SegNet, and U-Net for Semantic Segmentation of Synthetic Wafer Map Defect Patterns
Balachandar Jeganathan *
ASML, San Jose, CA, USA.
*Author to whom correspondence should be addressed.
Abstract
Wafer defect maps serve as a primary diagnostic tool for process engineers, enabling the visualization of spatial defect distributions and the identification of potential equipment or process issues. As technology nodes shrink and device densities increase, the volume of inspection data has grown exponentially, rendering manual inspection impractical and necessitating automated solutions for defect pattern recognition. Modern semiconductor manufacturing depends critically on automated wafer defect pattern detection to prevent yield loss excursions and maintain process control. Deep learning, particularly convolutional encoder–decoder architectures, has emerged as a transformative approach for anomaly detection and semantic segmentation of wafer map defect patterns. This review comprehensively examines the state of the art in applying deep convolutional neural networks, including Fully Convolutional Networks (FCN), SegNet, and U-Net to the detection and pixel-level segmentation of abnormal defect patterns on semiconductor wafers. The study analyzes methods for synthetic training data generation using Poisson point processes, evaluates the comparative performance of these architectures using intersection-over-union (IoU) metrics, and assesses their generalization capability to unseen defect patterns and real production wafer data. The review further discusses scalability considerations, the relationship between defect density and detection accuracy, and outlines future research directions, including vision transformers, transfer learning, and real-time deployment strategies. With approximately 25 recent references spanning 2015–2024, this article provides a thorough synthesis of methodologies, results, and open challenges for researchers and practitioners in semiconductor defect inspection. Future research should focus on bridging the synthetic-to-real domain gap through advanced data augmentation and domain adaptation techniques, incorporating attention mechanisms and transformer-based architectures, developing lightweight models for real-time edge deployment, and integrating explainable AI methods to enhance engineer trust and adoption.
Keywords: Deep learning, convolutional neural networks, encoder–decoder architectures, anomaly detection, semantic segmentation, semiconductor manufacturing, wafer defect patterns, yield enhancement